(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a two step method for annealing gate oxide.
(2) Description of the Prior Art
The formation of semiconductor devices typically starts with a bare wafer that is divided into a plurality of active regions and isolation regions. The isolation regions can be formed using such techniques as the growing of layers of Field Oxide (FOX) or by electrically isolating active regions by means of Shallow Trench Isolation (STI) regions. To provide stress relieve, a thin (15-100 um. thick) layer of oxide is thermally grown or CVD deposited over the upper surface of the substrate in the active areas. For the creation of MOS devices, a gate electrode is created, the layer of oxide under the gate forms the gate oxide. The gate electrode is then grown by the deposition, patterning and etching of a layer of polysilicon in the active region of the device. Lightly Doped Drain regions can be created immediately adjacent to the gate electrode, gate spacers are formed on the sides of the electrode. An implant can next be performed to introduce an impurity distribution in the source/drain regions of the gate electrode. Electrical contact is established as a final step with the source/drain regions and the top surface of the gate electrode.
As part of the preceding procedure, threshold voltage performance can be improved by a channel implant (of for instance boron concentrations of between about 10.sup.12 -10.sup.13 atoms/cm.sup.2 implanted with an energy of between about 50 and 100 keV), this after the layer of gate oxide has been created. The (boron) ions will penetrate the layer of gate oxide but will not penetrate the FOX layer for the isolation region and will form an electrical barrier between the source and the drain regions.
The growth of the gate oxide is a very critical step in the creation of the gate electrode. Proper device operation requires a layer of high quality oxide without contamination since even minor amount of impurities in the gate oxide may result in impaired breakdown and reliability of the gate electrode. Basic principles of operation of the gate electrode teach that the drain current of a MOS transistor is inversely proportional to the thickness of the gate oxide. Increased drain current results in improved (faster) device operation that imposes the requirement that the gate oxide must be as thin as possible. Device refresh cycle time is improved by thinner gate oxide. Before the gate oxide layer is deposited, the surface over which the layer is to be deposited must be made free of any contaminants or of any residual oxide. The substrate surface on which the gate oxide is created is therefore wet-etched to remove any residuals. As a further preparation of the surface on which the gate oxide is to be created, a sacrificial layer of oxide can first be grown, this layer of sacrificial oxide removes any dry-etch induced damage or unwanted nitride. This layer of sacrificial oxide is removed after which the layer of gate oxide is grown under extreme conditions of control, typically through dry oxidation in chlorine ambient. The main parameter in the growth of this high quality layer of oxide is the time required for the growth process, only through making this process a very slow process with a low growth rate can reasonable oxide be obtained.
With decreased gate electrode dimensions, device limitations imposed by these reduced dimensions must be removed. Short channel effects are removed by reduced junction depth for the source/drain regions and by reducing the thickness of the gate oxide. Extreme reduction of the gate oxide thickness, to for instance 50 Angstrom or even less, results in increased impact of electrically active impurities and to the diffusion of these impurities from the gate structure across the gate oxide into the active regions of the device. These impurities may, with a thinner gate oxide layer, also more readily migrate into the channel region of the transistor and affect the threshold voltage, a problem that is especially acute for boron or BF.sub.2 implanted devices (since boron/BF.sub.2 are P.sup.+ dopants). Decreased thickness of the gate oxide further causes increased electric field density and strength across the oxide to substrate interface causing concerns about oxide breakdown. This increased electric field strength can reach across the interface into the device channel region further raising concerns about hot carrier damage.
S. Wolf, Silicon Processing for the VSLI Era, Vol. 1, pg. 209 e.a. teaches that various techniques have been used to achieve reduced growth rate of thin oxide, such as dry oxidation, dry oxidation with HCl, trichloroethylene, TCE or trichloroethane, reduced pressure oxidation, a low temperature/high pressure oxidation and a rapid thermal processing under oxidation conditions. As examples are cited the growth of thin (less than 200 Angstrom) oxides in dry O.sub.2 at a temperature between about 780 and 980 degrees C. Specifically, a 100 Angstrom thick layer of oxide can be grown in this manner during a time of 30 minutes and at a temperature of 893 degrees C. Another example cited is the growth of thin oxide using LPCVD at reduced pressure of 0.25 to 2 Torr and a temperature of about 900 to 1000 degrees C. The reduction on pressure results in improved thickness control.
U.S. Pat. No. 5,811,334 teaches techniques for the cleaning procedures in preparation of the deposition of the oxide layer. One such procedure is a two step procedure; the first step designed to remove organic contaminants such as residual photoresist, the second step to remove trace metal particles and ionic contaminants. The first step generally requires immersing the wafer in a 70 to 85 degrees C. solution of H.sub.2 O--NH.sub.4 OH--H.sub.2 O.sub.2 ; the second step generally comprises immersing the wafer in a 75 to 85 degrees C. solution of H.sub.2 O--HCl--H.sub.2 O.sub.2. This process however has the disadvantage of roughing the substrate surface, which results in the deposition of lower quality oxides.
Irregularities in the thermal oxide layer may also result from irregularities on the substrate surface such as precipitates, dislocation, faults, defects, contaminants and improper bonds. These irregularities cause improper growth of the oxide layer on the substrate surface, this effect may be further aggravated if the substrate irregularities are the cause of irregular growth ("trap sites") of the oxide layer in the vicinity of the underlying disturbances. This can for instance result in local oxide thinning while trap sites may play the role of binding charged ions thereby further disrupting regular growth and deposition of the oxide. Charges accumulate in localized trap sites when the transistor is biased causing electrical breakdown of the oxide in the vicinity of the trap sites and thus affecting the threshold voltage of the oxide layer. The conventional anneal step is implemented to, as much as possible, negate the indicated negative affect by, among others, eliminating trap sites and other irregularities. Anneal can consist of a double anneal cycle. The first anneal cycle improves the surface of the silicon substrate and makes it better suited for the deposition of a high quality layer of oxide. The second anneal is more aimed at improving the quality of the created layer of oxide by removing irregularities or trap sites inside the oxide layer. The process of creating a layer of oxide may therefore by broken down in a pre-oxidation anneal and a post-oxidation anneal, both cycles of annealing to be performed under carefully controlled processing conditions of temperature, pressure, gas flow, etc.
In a typical thermal oxidation method, the substrate is thermally oxidized to form the substrate oxide film. The substrate is placed inside a quartz tube in a vertical or horizontal type heat treatment furnace. An oxidizing source such as oxygen with water vapor is fed into the quartz tube while the wafer is heated to about 1000 degrees C. The oxide layer formed is this manner is then further subjected to an annealing process, this typically in a dry ambient gas. Immediately after the annealing process, many dangling bonds are assumed to be present in the interface between the oxide film and the surface of the substrate. These dangling bonds are considered to be unstable states and the cause of increased surface recombinations, thus reducing the wafer lifetime. Other methods of forming oxidation layers are electromechanical anode oxidation and plasma reaction. The above-indicated method of thermal oxidation is an example of a wet oxidation method. Wet oxidation can also use vaporized H.sub.2 O as the oxidation medium. Dry oxidation methods use O.sub.2 and HCl gases to form the oxide layer. The dry oxidation method is the preferred method to form gate oxide layers since this method can better control the formation of a thin film and can obtain a high quality oxide.
Thinner oxide layers are increasingly affected by oxide layer breakdown phenomenon such as lattice defects caused by particles, carbon participates, stacking faults, metallic combinations and the contamination of the oxide film.
During the formation of an oxide layer on the surface of a substrate, the interface between the silicon and the oxide film extends into the surface of the substrate. This is because the oxygen atoms oxidize the silicon atoms. Approximately 44% of the overall oxide film penetrates below the surface of the substrate. Contaminants on the surface of the substrate, such as metal ions and natrium ions, penetrate the oxide film on the surface of the substrate thereby creating a new distribution and profile of the energy level within the oxide film. This shifting in electrical energy within the oxide layer has a deteriorating effect on the oxide layer (and therefore the device) reliability and its electrical characteristics.
The post-oxidation annealing process is applied to reduce the fixed charges in the formed oxide layer. Fixed charge density can for instance be reduced by annealing in nitrogen or argon at atmospheric pressure using a hot-wall annealing furnace at temperatures of about 900 degrees C. High temperature annealing however adversely affects the insulating and dielectric characteristics of oxide layer over extended periods of time. This effect has been connected with the thermal decomposition of oxide on silicon surfaces at elevated temperatures. Oxide decomposition can take the form of the generation of a volatile product, silicon monoxide (SiO) creating atomic voids in the oxide layer thereby affecting layer reliability and performance. The oxide layer may cease to be able to sustain the electric field that is required for proper device operation and will, as a consequence, fail to operate or fail prematurely.
U.S. Pat. No. 5,811,334 (Buller et al.) shows an H.sub.2 anneal of an oxide layer, see col. 4, lines 41-44.
U.S. Pat. No. 5,851,888 (Gardner et al.), U.S. Pat. No. 5,210,056 (Pong et al.) and U.S. Pat. No. 5,851,892 (Lojek et al.) show N.sub.2 anneals for a gate oxide.
U.S. Pat. No. 5,646,074 (Chen et al.) teaches a O.sub.2 anneal for a gate oxide.
U.S. Pat. No. 5,620,932 (Fujimaki) discloses a low temperature H.sub.2 anneal of an oxide layer.
U.S. Pat. No. 5,538,923 (Gardner) shows an N.sub.2 anneal.